Synthesis of Timed Circuits using BDDs

نویسندگان

  • Robert A. Thacker
  • Chris J. Myers
چکیده

This paper presents a tool which synthesizes timed circuits from reduced state graphs. Using timing information to reduce state graphs can lead to significantly smaller and faster circuits. The tool uses implicit techniques (binary decision diagrams) to represent these graphs. This allows us to synthesize larger, more complex systems which may be intractable with an explicit representation. We are also able to create a parameterized family of solutions, facilitating technology mapping.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Timed Circuit Synthesis Using Implicit Methods

The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification. This information is used throughout the synthesis procedure to optimize the design. In order to synthesize a timed circuit, it is necessary to explore the timed s...

متن کامل

BDD Ordering and Minimization Using Various Crossover Operators in Genetic Algorithm

Binary Decision Diagram (BDD) is a data structure which is extensively used for compact representation of Boolean functions. On a more abstract level, BDDs can be considered as a compressed representation of sets or relations. BDDs are extensively used in CAD software to synthesize circuits (logic synthesis) and in formal verification. Ordering of BDDs play a major role in reduction of nodes an...

متن کامل

B . Becker , R . E . Bryant , O . Coudert , Ch . Meinel ( Hrsg

s of the Talks 7 Probabilistic Analysis of Large Finite State Machines F. Somenzi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 On Improving OBDD-Based Verification in a Synthesis Environment W. Kunz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 On Computing the Maximum Power Cycle of Sequential Circuits A. Pardo . . . . . . . . . . . . . . . . . . . . . . . ...

متن کامل

Synthesis of Low-Power Digital Circuits Derived from Binary Decision Diagrams

| This paper introduces a novel method for synthesizing digital circuits derived from Binary Decision Diagrams (BDDs) that can yield to reduction in power dissipation. The power reduction is achieved by decreasing the switching activity in a circuit while paying close attention to information measures as an optimization criterion. We rst present the technique of e cient BDDbased computation of ...

متن کامل

Timed state space exploration using POSETs

| This paper presents a new timing analysis algorithm for eecient state space exploration during the synthesis of timed circuits or the veriication of timed systems. The source of the computational complexity in the synthesis or veriication of a timed system is in nding the reachable timed state space. We introduce a new algorithm which utilizes geometric regions to represent the timed state sp...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1998